Hierarchical Gate-level Veriication of Speed-independent Circuits Hierarchical Gate-level Veriication of Speed-independent Circuits

This paper presents a method for the veriication of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the veriication time complexity depend only on the number of state signals (C elements, RS ip-ops) of the circuit. Despite the reduction to complex gates, veriication is kept exact. The speciication of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical veriication.